參數(shù)資料
型號(hào): MC74HC533A
廠商: Motorola, Inc.
英文描述: Octal 3-State Inverting Transparent Latch
中文描述: 八路三態(tài)反相透明鎖存器
文件頁數(shù): 3/7頁
文件大?。?/td> 146K
代理商: MC74HC533A
MC54/74HC533A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Voltages Referenced to GND)
μ
A
±
0.5
±
5.0
25 C
±
0.1
6.0
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
Maximum Three–State Leakage
Current
IOZ
Unit
μ
A
±
10
125 C
±
1.0
85 C
±
1.0
V
Test Conditions
Vin = VCC or GND
Parameter
Symbol
Iin
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
Maximum Input Leakage Current
6.0
4.0
40
Maximum Quiescent Supply
6.0
160
μ
A
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
b l
Parameter
Fig.
V
1, 5
2.0
3.0
4.5
6.0
21
Guaranteed Limit
U i
125 C
tPLH
tPHL
Maximum Propagation Delay, Input D to Q
V
125
80
25
– 55 to
25 C
155
110
85 C
190
130
38
32
ns
Unit
31
26
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
2, 5
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
3, 6
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
3, 6
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
1, 5
2.0
3.0
4.5
75
27
15
95
32
19
110
36
22
ns
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
bl d O
Typical @ 25
°
C, VCC = 5.0 V
36
pF
相關(guān)PDF資料
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