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參數(shù)資料
| 型號： | MC74HC51N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2-Wide, 2-Input/2-Wide, 3-Input AND-NOR Gates |
| 中文描述： | HC/UH SERIES, DUAL 6-INPUT AND-OR-INVERT GATE, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 146K |
| 代理商： | MC74HC51N |
MC74HC51
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
25
38
6.0
13
31
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Section)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
23
pF
Figure 1. Switching Waveforms
tr
VCC
GND
90%
50%
10%
90%
50%
10%
INPUT
OUTPUT Y
tPHL
tPLH
t tTHL
tTLH
* Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
tf
EXPANDED LOGIC DIAGRAM
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
1
12
13
9
10
11
2
3
4
5
Y1
Y2
8
6
PIN 14 = VCC
PIN 7 = GND
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