參數(shù)資料
型號: MC74HC4353
廠商: Motorola, Inc.
英文描述: Analog Multiplexers/Demultiplexers with Address Latch
中文描述: 模擬多路復(fù)用器/解復(fù)用器的地址鎖存
文件頁數(shù): 4/13頁
文件大?。?/td> 477K
代理商: MC74HC4353
MC54/74HC4351 MC54/74HC4353
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
Symbol
Ron
Parameter
Maximum “ON” Resistance
Test Conditions
V
V
25 C
125 C
280
140
Vin = VIL or VIH
2.0 mA (Figures 1, 2)
Vin = VIL or VIH
VIS = 1/2 (VCC – VEE)
VIO = VCC – VEE
Switch Off (Figure 3)
Switch Off (Figure 4)
4.5
6.0
0.0
– 6.0
190
100
85 C
240
125
Unit
4.5
0.0
150
190
230
Resistance Between Any Two
4.5
– 4.5
12
15
18
Current, Any One Channel
HC4351
HC4353
(Figure 5)
6.0
6.0
– 6.0
– 6.0
0.2
0.1
2.0
1.0
4.0
2.0
HC4351
HC4353
6.0
6.0
– 6.0
– 6.0
0.2
0.1
2.0
1.0
4.0
2.0
V
Guaranteed Limit
VCC
– 55 to
25 C
74
63
79
110
94
(Figure 9)
4.5
6.0
93
6.0
10
13
tPLH,
Maximum Propagation Delay, Latch Enable to Analog Output
2.0
325
410
485
15
tPHZ
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
290
58
365
73
435
ns
tPZH
(Figure 11)
4.5
69
87
103
87
ns
50
50
HC4353
1.0
1.0
1.0
50
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Feedthrough
CPD
Power Dissipation Capacitance (Per Package) (Figure 14)*
Typical @ 25
°
C, VCC = 5.0 V
45 (HC4351)
45 (HC4353)
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
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