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參數(shù)資料
| 型號(hào)： | MC74HC4351N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Single Operational Amplifier; Package: DIP; No of Pins: 8; Container: Rail |
| 中文描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 294K |
| 代理商： | MC74HC4351N |
MC74HC4351A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
10
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = + 5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example, the
difference between VCC and VEE is ten volts. Therefore, us-
ing the configuration in Figure 16, a maximum analog signal
of ten volts peak–to–peak can be controlled. Unused analog
inputs/outputs may be left floating (i.e., not connected). How-
ever, tying unused analog inputs and outputs to VCC or GND
through a low value resistor helps minimize crosstalk and
feedthrough noise that may be picked up by an unused
switch.
Although used here, balanced supplies are not a require-
ment. The only constraints on the power supplies are that:
VCC – GND = 2 to 6 volts
VEE – GND = 0 to – 6 volts
VCC – VEE = 2 to 12 volts
and VEE
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 17. These diodes should be able to absorb the maxi-
mum anticipated current surges during clipping.
GND
Figure 16. Application Example
Figure 17. External Germanium or
Schottky Clipping Diodes
ANALOG
SIGNAL
ON
20
+5 V
ANALOG
SIGNAL
+ 5 V
– 5 V
+ 5 V
– 5 V
TO EXTERNAL CMOS
CIRCUITRY
0 TO 5 V DIGITAL
SIGNALS
ON/OFF
9
10
20
VCC
VEE
Dx
VEE
Dx
VCC
Dx
8
9
10
7
–5 V
+5 V
15
13
12
11
VEE
VCC
Dx
Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs
a. Using Pull–Up Resistors
b. Using HCT Interface
ANALOG
SIGNAL
ON/OFF
20
+ 5 V
ANALOG
SIGNAL
+ 5 V
VEE
+ 5 V
VEE
R
*
LSTTL/NMOS
CIRCUITRY
+ 5 V
* 2 k
≤
R
≤
10 k
ANALOG
SIGNAL
ON/OFF
20
+ 5 V
ANALOG
SIGNAL
+ 5 V
VEE
+ 5 V
VEE
LSTTL/NMOS
CIRCUITRY
+ 5 V
HCT
BUFFER
8
9
10
7
VEE
VCC
15
13
12
11
R
R
R
8
9
10
7
VEE
VCC
15
13
12
11
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