參數(shù)資料
型號: MC74HC4052A
廠商: Motorola, Inc.
英文描述: ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
中文描述: 模擬多路復(fù)用器/解復(fù)用器
文件頁數(shù): 5/15頁
文件大?。?/td> 199K
代理商: MC74HC4052A
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
b l
Parameter
VCC
V
Guaranteed Limit
U i
Unit
–55 to 25
°
C
85
°
C
125
°
C
tPLH,
tPHL
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
Cin
CI/O
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
10
10
pF
Maximum Capacitance
Analog I/O
35
35
35
pF
(All Switches Off)
Common O/I: HC4051A
HC4052A
HC4053A
130
80
50
130
80
50
130
80
50
Feedthrough
1.0
1.0
1.0
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
Typical @ 25
°
C, VCC = 5.0 V, VEE = 0 V
45
80
45
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
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