TIMING REQUIREMENTS (Input tr = " />
參數(shù)資料
型號(hào): MC74HC4040ADTR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 7/11頁(yè)
文件大?。?/td> 0K
描述: IC COUNTER 12STAGE BIN 16-TSSOP
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 12
復(fù)位: 異步
計(jì)數(shù)速率: 50MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
MC74HC4040A
http://onsemi.com
5
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
55 to 25°C
≤85°C
≤125°C
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negativeedge triggering clock input. A hightolow
transition on this input advances the state of the counter.
Reset (Pin 11)
Activehigh reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Activehigh outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
Clock
Q1
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH
tTHL
Clock
VCC
GND
tw
trec
50%
Figure 3.
Reset
VCC
GND
50%
Any Q
50%
tPHL
Figure 4.
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