TIMING REQUIREMENTS (Input tr = t" />
參數(shù)資料
型號: MC74HC393ADTR2
廠商: ON Semiconductor
文件頁數(shù): 7/11頁
文件大?。?/td> 0K
描述: IC COUNTER RPPL DUAL 4ST 14TSSOP
產(chǎn)品變化通告: Product Obsolescence 24/Jan/2011
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 2
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)數(shù)速率: 50MHz
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
MC74HC393A
http://onsemi.com
5
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flipflops are toggled and the
counter state advances on hightolow transitions of the
clock input.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
CONTROL INPUTS
Reset (Pins 2, 12)
Activehigh, asynchronous reset. A separate reset is
provided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
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