參數(shù)資料
型號(hào): MC74HC390N
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 通用總線(xiàn)功能
英文描述: Dual 4-Stage Binary Ripple Counter with ±2and ±5 Sections
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 216K
代理商: MC74HC390N
MC54/74HC390
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
6
APPLICATIONS INFORMATION
Each half of the MC54/74HC390 has independent
÷
2 and
÷
5 sections (except for the Reset function). The
÷
2 and
÷
5
counters can be connected to give BCD or bi–quinary (2–5)
count sequences. If Output QA is connected to the Clock B
input (Figure 4), a decade divider with BCD output is
obtained. The function table for the BCD count sequence is
given in Table 1.
To obtain a bi–quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty cycle
output. The bi–quinary count sequence function table is
given in Table 2.
Table 1. BCD Count Sequence*
Count
Output
QD
L
L
L
L
L
L
L
L
H
H
QC
L
L
L
L
H
H
H
H
L
L
QB
L
L
H
H
L
L
H
H
L
L
QA
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
* QA connected to Clock B input.
Table 2. Bi–Quinary Count Sequence**
Count
Output
QA
L
L
L
L
L
H
H
H
H
H
QD
L
L
L
L
H
L
L
L
L
H
QC
L
L
H
H
L
L
L
H
H
L
QB
L
H
L
H
L
L
H
L
H
L
0
1
2
3
4
8
9
10
11
12
**QD connected to Clock A input.
CONNECTION DIAGRAMS
1, 15
÷
2
COUNTER
CLOCK A
RESET
Figure 4. BCD Count
Figure 5. Bi-Quinary Count
÷
2
COUNTER
÷
5
COUNTER
÷
5
COUNTER
CLOCK B
CLOCK A
RESET
CLOCK B
1, 15
QA
QB
QC
QD
3, 13
5, 11
6, 10
7, 9
4, 12
2, 14
QA
QB
QC
QD
3, 13
5, 11
6, 10
7, 9
4, 12
2, 14
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