參數(shù)資料
型號(hào): MC74HC390D
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual 4-Stage Binary Ripple Counter with ±2and ±5 Sections
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
封裝: 0.150 INCH, PLASTIC, SOIC-16
文件頁數(shù): 3/8頁
文件大小: 216K
代理商: MC74HC390D
MC54/74HC390
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 3)
4.5
27
18
6.0
20
22
31
tPLH,
Maximum Propagation Delay, Clock A to QC
2.0
290
365
26
435
ns
tPHL
(Figures 1 and 3)
4.5
26
39
6.0
31
33
48
tPLH,
Maximum Propagation Delay, Clock B to QD
2.0
6.0
130
22
165
39
195
33
ns
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
165
33
205
28
250
50
ns
(Figures 1 and 3)
4.5
15
41
22
Cin
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
10
19
10
pF
10
CPD
Power Dissipation Capacitance (Per Counter)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
35
pF
Symbol
Parameter
V
25 C
Unit
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
4.5
50
10
85 C
125 C
75
15
ns
(Figure 1)
4.5
16
65
13
24
6.0
21
20
32
tf, tf
Maximum Input Rise and Fall Times
2.0
1000
1000
26
1000
ns
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