參數(shù)資料
型號: MC74HC390AD
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDSO16
封裝: SOIC-16
文件頁數(shù): 4/8頁
文件大?。?/td> 216K
代理商: MC74HC390AD
MC54/74HC390
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the
÷
2 counter; Clock B is the
clock input to the
÷
5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip–flops, and forces QA through
QD low.
OUTPUTS
QA (Pins 3, 13)
Output of the
÷
2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the
÷
5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.
SWITCHING WAVEFORMS
Q
tr
tf
tPLH
tPHL
tTLH
tTHL
VCC
GND
CLOCK
10%
10%
50%
1/fmax
tw
trec
RESET
Figure 1.
Figure 2.
VCC
GND
VCC
GND
10%
90%
Q
CLOCK
50%
50%
50%
tPHL
tw
TEST CIRCUIT
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
相關PDF資料
PDF描述
MC74HC390ADR2 Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
MC74HC390ADT Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
MC74HC390AN Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
MC74HC390D Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
MC74HC390N Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections
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