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參數(shù)資料
| 型號(hào)： | MC74HC354N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| 中文描述： | HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MC74HC354N |
MC54/74HC354
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
FUNCTION TABLE
Address Latch Contents #
Inputs
Outputs
A2
A1
A0
Data–Latch
Enable
OE1
OE2
OE3
Y
Y
Description
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
X
X
L
Z
Z
Z
Z
Z
Z
Outputs in High–Impedance States
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L
H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Data–Latch is Transparent
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
D0n
D1n
D2n
D3n
D4n
D5n
D6n
D7n
D0n
D1n
D2n
D3n
D4n
D5n
D6n
D7n
New Data is Stored in Data–Latch and is
Not Alterable
# Represents bits in Address–Latch. See Address–Latch Enable pin description.
X = Don’t Care; Z = High Impedance; D0–D7 = the data at inputs D0 through D7; D0n–D7n = the data present at inputs D0 through D7 when the
Data–Latch Enable pin was taken high.
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
tr
Any Input
Y or Y
VCC
GND
90%
10%
tf
90%
10%
tTLH
tTHL
D0–D7
A0–A2
Y or Y
VCC
GND
tPHL
tPLH
50%
50%
VALID
VALID
Figure 3.
Address–
Latch Enable
Y or Y
VCC
GND
50%
tPLH
tPHL
tw
50%
Figure 4.
OE1, OE2
Y or Y
VCC
GND
tPZH
50%
50%
Y or Y
50%
tPHZ
tPZL
tPLZ
High
Impedance
VOL
VOH
High
Impedance
OE3
10%
90%
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