- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371064 > MC74HC299N (MOTOROLA INC) TIE WING PUSH MOUNT STD NAT 7.8,1 PDF資料下載
參數(shù)資料
| 型號： | MC74HC299N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | TIE WING PUSH MOUNT STD NAT 7.8,1 |
| 中文描述： | HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 268K |
| 代理商： | MC74HC299N |
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
FUNCTION TABLE
Inputs
Response
Mode
Reset
Mode
Select
Output
Enables
Clock
Serial
Inputs
PA/QA
PB/QB
PC/QC
PD/QD
PE/QE
PF/QF
PG/QG
PH/QH
S2
S1
OE1
OE2
DA
DH
QA
′
QH
′
Reset
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
QA through QH = Z
Shift
Right
H
H
H
L
L
L
H
H
H
H
X
L
X
H
L
D
D
D
X
X
X
Shift Right: QA through QH = Z; DA
Shift Right: QA through QH = Z; DA
Shift Right: DA
FA = QA; FA
FA; FA
FA; FA
FB; etc.
FB; etc.
D
D
D
QG
QG
QG
FB = QB; etc.
Shift
Left
H
H
H
H
H
H
L
L
L
H
X
L
X
H
L
X
X
X
D
D
D
Shift Left: QA through QH = Z; DH
Shift Left: QA through QH = Z; DH
Shift Left: DH
FH = QH; FH
FH; FH
FH; FH
FG = QG; etc.
FG; etc.
FG; etc.
QB
QB
QB
D
D
D
Parallel
Load
H
H
H
X
X
X
X
Parallel Load: PN
FN
PA
PH
Hold
H
H
H
L
L
L
L
L
L
H
X
L
X
H
L
X
X
X
X
X
X
X
X
X
Hold: QA through QH = Z; FN = FN
Hold: QA through QH = Z; FN = FN
Hold: QN = QN
PA
PA
PA
PH
PH
PH
Z = high impedance
D = data on serial input
F = flip–flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential
operation or clearing of the register is not affected.
PIN DESCRIPTIONS
DATA INPUTS
SA (Pin 11)
Serial data input (Shift Right). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
low and S1 is high (shift right mode).
SH (Pin 18)
Serial data input (Shift Left). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
high and S1 is low (shift left mode).
PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port inputs. Data on these pins can be paral-
lel loaded into the shift register on the rising edge of Clock
when both S1 and S2 are high. For any other combination of
S1 and S2, these pins serve as the outputs of the shift
register.
CONTROL INPUTS
Clock (Pin 12)
Clock input. A low–to–high transition on this pin shifts the
data at each stage to the next stage (shift right or left mode)
or loads the data at the parallel data inputs into the shift reg-
ister (parallel load mode).
OE1, OE2 (Pins 2, 3)
Active–low output enables. When both OE1 and OE2 are
low, the Outputs QA through QH are enabled. When one or
both output enables are high, the outputs are forced to the
high–impedance state; however, sequential operation or
clearing of the register is not affected.
Reset (Pin 9)
Active–low reset. A low on this pin resets all stages of the
register to a low level. The reset operation is asynchronous.
S1, S2 (Pins 1, 19)
Mode select inputs. The levels present at these pins deter-
mine the shift register’s mode of operation:
S1 = S2 = Low. Hold.
S1 = Low, S2 High. Shift left.
S1 = High, S2 Low. Shift right.
S1 = S2 = High. Parallel load.
OUTPUTS
QA
′
, QH
′
(Pins 8, 17)
Serial data outputs. These are the outputs of the first and
last stages of the shift register, respectively. These outputs
are not 3–state outputs and have standard drive capabilities.
QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port outputs. Shifted data is present at these
pins when OE1 and OE2 are low. For all other combinations
of OE1 and OE2 these outputs are in the high–impedance
state.
相關PDF資料 |
PDF描述 |
|---|---|
| MC74HC299 | 8-Bit Bidirectional Universal Shift Register with Parallel I/O |
| MC74HC30 | 8-Input NAND Gate High-Performance Silicon-Gate CMOS |
| MC74HC365 | Hex 3-State Noninverting Buffer with Common Enables |
| MC74HC365AD | Hex 3-State Noninverting Buffer with Common Enables |
| MC74HC365ADT | Hex 3-State Noninverting Buffer with Common Enables |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC30ADG | 功能描述:邏輯門 IC 8-IN NAND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC30ADR2G | 功能描述:邏輯門 IC 8-IN NAND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC30ADTG | 功能描述:邏輯門 IC 8-IN NAND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC30ADTR2G | 功能描述:邏輯門 IC 8-IN NAND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC30DT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。