參數(shù)資料
型號(hào): MC74HC299DW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 8-Bit Bidirectional Universal Shift Register with Parallel I/O
中文描述: HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20
封裝: 0.300 INCH, PLASTIC, SOIC-20
文件頁(yè)數(shù): 3/8頁(yè)
文件大小: 268K
代理商: MC74HC299DW
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
(Figures 1 and 5)
4.5
25
17
6.0
29
20
43
tPLH,
Maximum Propagation Delay, Clock to QA thru QH
2.0
160
200
37
240
ns
(Figures 2 and 5)
4.5
35
53
6.0
32
44
48
tPLZ,
Maximum Propagation Delay, OE1, OE2, S1, or S2 to QA thru QH
2.0
6.0
150
26
190
41
225
38
ns
tPZH
(Figures 3 and 6)
2.0
4.5
150
30
190
33
225
45
ns
(Figures 1 and 5)
4.5
12
38
18
tTLH,
Maximum Output Transition Time, QA
or QH
2.0
6.0
75
13
15
110
19
ns
Maximum Input Capacitance
10
95
16
10
pF
Maximum Three–State Output Capacitance
15
10
15
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
15
CPD
Power Dissipation Capacitance (Per Package)*, Outputs Enabled
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
240
pF
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