參數(shù)資料
型號: MC74HC259AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 8-Bit Addressable Latch 1-of-8 Decoder
中文描述: HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 3/8頁
文件大?。?/td> 246K
代理商: MC74HC259AN
MC54/74HC259A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
0.1
0.1
0.1
4.5
|Iout|
20
μ
A
Voltage
5.2 mA
0.26
0.33
0.40
Iin
ICC
Maximum Input Leakage Current
Vin = VCC or GND
Vin = VCC or GND
|Iout|
6.0
6.0
±
0.1
±
1.0
±
1.0
μ
A
Maximum Quiescent Supply
6.0
4
160
μ
A
40
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
VCC
Guaranteed Limit
– 55 to
4.5
32
42
4.5
32
32
45
4.5
32
40
45
4.5
22
40
32
(Figures 1 and 6)
3.0
4.5
27
15
26
36
22
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
32
19
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
30
pF
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