TIMING REQUIREMENTS (CL
參數(shù)資料
型號: MC74HC161ADR2G
廠商: ON Semiconductor
文件頁數(shù): 12/15頁
文件大?。?/td> 0K
描述: IC COUNTER 4BIT PRESET 16SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時: 同步
計(jì)數(shù)速率: 167MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 帶卷 (TR)
MC74HC161A, MC74HC163A
http://onsemi.com
6
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Figure
VCC
V
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
tsu
Minimum Setup Time,
Preset Data Inputs to Clock
2.0
3.0
4.5
6.0
40
20
15
12
60
30
20
18
80
40
30
20
ns
tsu
Minimum Setup Time,
Load to Clock
2.0
3.0
4.5
6.0
60
25
15
12
75
30
20
18
90
40
30
20
ns
tsu
Minimum Setup Time,
Reset to Clock (HC163A Only)
2.0
3.0
4.5
6.0
60
25
20
17
75
30
25
23
90
40
35
25
ns
tsu
Minimum Setup Time,
Enable T or Enable P to Clock
2.0
3.0
4.5
6.0
80
35
20
17
95
40
25
23
110
50
35
25
ns
th
Minimum Hold Time,
Clock to Load or Preset Data Inputs
2.0
3.0
4.5
6.0
3
ns
th
Minimum Hold Time,
Clock to Reset (HC163A Only)
2.0
3.0
4.5
6.0
3
ns
th
Minimum Hold Time,
Clock to Enable T or Enable P
2.0
3.0
4.5
6.0
3
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
trec
Minimum Recovery Time,
Load Inactive to Clock
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
tw
Minimum Pulse Width,
Clock
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tw
Minimum Pulse Width,
Reset (HC161A Only)
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
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