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參數(shù)資料
| 型號： | MC74HC11 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual J-K Flip-Flop with Set and Reset |
| 中文描述： | 雙JK觸發(fā)器的設(shè)置和復(fù)位 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 211K |
| 代理商： | MC74HC11 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC112 is identical in pinout to the LS112. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip–flop is negative–edge clocked and has active–low asynchro-
nous Set and Reset inputs.
The HC112 is identical in function to the HC76, but has a different pinout.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Similar in Function to the LS112 Except When Set and Reset are Low
Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
LOGIC DIAGRAM
RESET 1
J1
CLOCK 1
K1
SET 1
Q1
Q1
Q2
Q2
RESET 2
J2
CLOCK 2
K2
SET 2
4
2
1
3
15
6
5
9
7
14
11
13
12
10
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Reset Clock
PIN ASSIGNMENT
Outputs
Q
Set
J
K
Q
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
H
L
L*
L
H
L*
No Change
L
H
Toggle
No Change
No Change
No Change
H
L
L
H
* Both outputs will remain low as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
K2
CLOCK 2
RESET 2
RESET 1
VCC
Q2
SET 2
J2
K1
CLOCK 1
J1
SET 1
Q1
Q1
Q2
GND
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
MC74HCXXXDT
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HC112DT | Dual J-K Flip-Flop with Set and Reset |
| MC74HC112N | Dual J-K Flip-Flop with Set and Reset |
| MC74HC11AD | Triple 3-Input AND Gate |
| MC74HC11ADT | Triple 3-Input AND Gate |
| MC74HC11AN | Triple 3-Input AND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC112ADG | 功能描述:觸發(fā)器 DUAL J-K FLIP FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC74HC112ADR2G | 功能描述:觸發(fā)器 DUAL J-K FLIP FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC74HC112ADTG | 功能描述:觸發(fā)器 DUAL J-K FLIP FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC74HC112ADTR2G | 功能描述:觸發(fā)器 DUAL J-K FLIP FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC74HC112FR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
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