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參數(shù)資料
| 型號(hào)： | MC74F569N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-BIT BIDIRECTIONAL COUNTERS(WITH 3-STATE OUTPUTS) |
| 中文描述： | F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP20 |
| 封裝： | 738-03 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MC74F569N |
4-220
FAST AND LS TTL DATA
4-BIT BIDIRECTIONAL COUNTERS
(WITH 3-STATE OUTPUTS)
The MC54/74F568 and MC54/74F569 are fully synchronous, reversible
counters with 3-state outputs. The F568 is a BCD decade counter; the F569
is a binary counter. They feature preset capability for programmable opera-
tion, carry lookahead for easy cascading, and a U/D input to control the direc-
tion of counting. For maximum flexibility there are both synchronous and mas-
ter asynchronous reset inputs as well as both Clocked Carry (CC) and
Terminal Count (TC) outputs. All state changes except Master Reset are initi-
ated by the rising edge of the clock. A HIGH signal on the Output Enable (OE)
input forces the output buffers into the high impedance state but does not pre-
vent counting, resetting or parallel loading.
4-Bit Bidirectional Counting
F568 Decade Counter
F569 Binary Counter
Synchronous Counting and Loading
Lookahead Carry Capability for Easy Cascading
Preset Capability for Programmable Operation
3-State Outputs for Bus Organized Systems
Master Reset (MR) Overrides All Other Inputs
Synchronous Reset (SR) Overrides Counting and Parallel Loading
CONNECTION DIAGRAM
CC
OE
O0
18
17
16
15
14
13
1
2
3
4
P1
5
6
7
20
19
8
VCC
U/D
TC
O2
O1
O3
CP
P0
P2
P3
CEP
MR
9
10
GND
SR
12
11
CET
PE
MC54/74F568
MC54/74F569
4-BIT
BIDIRECTIONAL
COUNTERS
(WITH 3-STATE OUTPUTS)
FAST
SCHOTTKY TTL
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXDW
Ceramic
Plastic
SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
LOGIC SYMBOL
11
3
4
PE
P0
P1
P2
P3
U/D
CEP
CET
CP
OE
MR SR
O0O1
O2
O3
CC
TC
5
6
18
19
8
9
16
15
14
13
1
7
12
2
17
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