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參數(shù)資料
| 型號： | MC74F194N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| 中文描述： | F/FAST SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 81K |
| 代理商： | MC74F194N |
4-101
FAST AND LS TTL DATA
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The MC74F194 is a high-speed 4-bit bidirectional universal shift register. As
a high-speed multifunctional, sequential building block, it is useful in a wide
variety of applications. It may be used in serial-serial, shift left, shift right,
serial-parallel, parallel-serial, and parallel-parallel data register transfers. The
F194 is similar in operation to the S195 universal shift register, with added
features of shift left without external connections and hold (do nothing) modes
of operation.
Typical Shift Frequency of 150 MHz
Asynchronous Master Reset
Hold (Do Nothing) Mode
Fully Synchronous Serial or Parallel Data Transfers
FUNCTIONAL DESCRIPTION
The F194 contains four edge-triggered D flip-flops and the necessary
interstage logic to synchronously perform shift right, shift left, parallel load and
hold operations. Signals applied to the Select (S0, S1) inputs determine the
type of operation, as shown in the Function Table. Signals on the Select,
Parallel data (P0–P3) and Serial data (DSR, DSL) inputs can change when the
clock is in either state, provided only that the recommended setup and hold
times, with respect to the clock rising edge, are observed. A LOW signal on
Master Reset (MR) overrides all other inputs and forces the outputs LOW.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
MR
Q0
Q1
Q2
Q3
S1
CP
S0
DSR
P0
P1
P2
P3
DSL
GND
CONNECTION DIAGRAM
FUNCTION TABLE
Mode
Inputs
Outputs
Operating
MR
L
S1
X
S0
X
DSR
X
DSL
X
Pn
X
Q0
L
Q1
L
Q2
L
Q3
L
Reset
Hold
H
I
I
X
X
X
q0
q1
q1
L
H
q1
q2
q2
q0
q0
p1
q2
q3
q3
q1
q1
p2
q3
L
H
Shift Left
H
H
h
h
I
I
X
X
I
X
X
h
Shift Right
H
H
I
I
h
h
I
X
X
X
X
q2
q2
p3
h
Parallel Load
I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
pn, qn = Lower case letters indicate the state of the referenced input or output one setup
time prior to the LOW-to-HIGH clock transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
H
h
h
X
X
pn
p0
MC74F194
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
FAST
SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
MC74FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
11 10
9
2
3
4
5
6
7
1
15
14
13
12
MR
Q0
Q1
Q2
Q3
DSR
P0
P1
P2
P3
DSL
CP S1S0
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