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參數(shù)資料
| 型號(hào)： | MC74F1803 |
| 廠商： | Motorola, Inc. |
| 英文描述： | CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS |
| 中文描述： | 時(shí)鐘驅(qū)動(dòng)器，四D型倒裝與時(shí)滯匹配傳輸次浮點(diǎn)運(yùn)算 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 78K |
| 代理商： | MC74F1803 |
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from Logic Marketing
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
1
7/95
REV 4
!%!
$ &
# # ! # &"
The MC74F1803 is a high–speed, low–power, quad D–type flip–flop
featuring separate D–type inputs and inverting outputs with closely matched
propagation delays. With a buffered clock (CP) input that is common to all
flip–flops, the MC74F1803 is useful in high–frequency systems as a clock
driver, providing multiple outputs that are synchronous. Because of the
matched propagation delays, the duty cycles of the output waveforms in a
clock driver application are symmetrical within 2.0 nanoseconds.
Edge–Triggered D–Type Inputs
Buffered Positive Edge–Triggered Clock
Matched Outputs for Synchronous Clock Driver Applications
Outputs Guaranteed for Simultaneous Switching
Pinout: 14–Lead Plastic
(Top View)
14
13
12
11
10
9
1
2
3
O0
4
D0
5
D1
6
O1
8
7
VCC
NC
O3
D3
D2
O2
CP
GND
NC
GND
LOGIC DIAGRAM
CP
D0
CP
D
Q
O0
D1
CP
D
Q
O1
D2
CP
D
Q
O2
D3
CP
D
Q
O3
VCC = Pin 14; GND = Pins 1,7; NC = Pins 2, 13
NOTE: This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays
CLOCK DRIVER QUAD
D–TYPE FLIP–FLOP WITH
MATCHED PROPAGATION
DELAYS
N SUFFIX
PLASTIC
CASE 646–06
14
1
14
1
D SUFFIX
SOIC
CASE 751A–03
LOGIC SYMBOL
8
4
5
10
11
3
6
9
12
D0
D1
D2
D3
O1
O0
O2
O3
CP
VCC = PIN 14
GND = PINS 1 AND 7
NC = PINS 2 AND 13
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