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參數(shù)資料
| 型號： | MC74F174N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Supply Voltage Supervisor w/Watchdog input and manual reset 5-SOT-23 -40 to 85 |
| 中文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 59K |
| 代理商： | MC74F174N |
4-86
FAST AND LS TTL DATA
HEX D FLIP-FLOP WITH
MASTER RESET
The MC54/74F174 is a high-speed hex D flip-flop. The device is used pri-
marily as a 6-bit edge-triggered storage register. The device has a Master Re-
set to simultaneously clear all flip-flops.
The F174 consists of six edge-triggered D flip-flops with individual D inputs
and Q outputs. The Clock (CP) and Master Reset (MR) are common to all
flip-flops. The state of each D input, one setup time before low-to-high clock
transition, is transferred to the corresponding flig-flop’s Q output. A LOW input
to the Master Reset (MR) will force all outputs LOW independent of Clock or
Data inputs. The F174 is useful for applications where only the true output is
required and the Clock and Master Reset are common to all storage elements.
Six Edge-triggered D-type Inputs
Buffered Positive Edge-triggered Common Clock
Buffered, Asynchronous Common Reset
CONNECTION DIAGRAM DIP
(TOP VIEW)
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
Q5
D5
D4
Q4
D3
Q3
CP
MR
Q0
D0
D1
Q1
D2
Q2
GND
FUNCTION TABLE
Inputs
Outputs
@ tn, MR = H
@ tn + 1
Dn
Qn
H
H
L
L
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
H = HIGH Voltage Level
L = LOW Voltage Level
MC54/74F174
HEX D FLIP-FLOP
WITH MASTER RESET
FAST
SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
MC54FXXXJ
MC74FXXXN
MC74FXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
14
13
11
6
4
3
12
10
7
5
2
9
1
15
D5
D4
D3
D2
D1
D0
Q5
Q4
Q3
Q2
Q1
Q0
CP
MR
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