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參數(shù)資料
| 型號(hào)： | MC74ACT323N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-INPUT UNIVERSAL SHIFT/ STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS |
| 中文描述： | ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 302K |
| 代理商： | MC74ACT323N |
MC74AC323 MC74ACT323
5-3
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC323/74ACT323 contains eight edge-
triggered D-type flip-flops and the interstage logic necessary
to perform synchronous reset, shift left, shift right, parallel load
and hold operations. The type of operation is determined by S0
and S1 as shown in the Mode Select Table. All flip-flop outputs
are brought out through 3 state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All other
state changes are also initiated by the LOW-to-HIGH CP
transition. Inputs can change when the clock is in either state
provided only that the recommended setup and hold times,
relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
TRUTH TABLE
Inputs
Response
SR
S1
S0
CP
L
H
H
H
H
X
H
L
H
L
X
H
H
L
L
Synchronous Reset; Q0 – Q7 = LOW
Parallel Load; I/On
→
Qn
Shift Right; DS0
→
Q0, Q0
→
Q1, etc.
Shift Left; DS7
→
Q7, Q7
→
Q6, etc.
Hold
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±
20
V
DC Output Voltage (Referenced to GND)
V
DC Input Current, per Pin
mA
DC Output Sink/Source Current, per Pin
±
50
mA
DC VCC or GND Current per Output Pin
Storage Temperature
±
50
mA
–65 to +150
°
C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
′
AC
′
ACT
2.0
5.0
6.0
V
4.5
5.0
5.5
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
0
VCC
V
′
AC Devices except Schmitt Inputs
VCC @ 3.0 V
VCC @ 4.5 V
VCC @ 5.5 V
VCC @ 4.5 V
VCC @ 5.5 V
150
tr, tf
Input Rise and Fall Time (Note 1)
40
ns/V
25
tr, tf
Input Rise and Fall Time (Note 2)
′
ACT Devices except Schmitt Inputs
10
ns/V
8.0
TJ
TA
IOH
IOL
Junction Temperature (PDIP)
140
°
C
Operating Ambient Temperature Range
–40
25
85
°
C
Output Current — High
–24
mA
Output Current — Low
24
mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
相關(guān)PDF資料 |
PDF描述 |
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| MC74AC323N | 8-INPUT UNIVERSAL SHIFT/ STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS |
| MC74AC353D | DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS |
| MC74ACT353 | DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS |
| MC74ACT353D | DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS |
| MC74ACT353N | DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS |
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