參數(shù)資料
型號(hào): MC74ACT273N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: OCTAL D FLIP-FLOP
中文描述: ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 1/7頁
文件大小: 187K
代理商: MC74ACT273N
5-1
FACT DATA
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-
flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW
voltage level on the MR input. The device is useful for applications where the true
output only is required and the Clock and Master Reset are common to all storage
elements.
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
ACT273 Has TTL Compatible Inputs
19
20
18
17
16
15
14
2
1
3
4
5
6
7
VCC
13
8
12
9
11
10
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
PIN NAMES
D0–D7
MR
CP
Q0–Q7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
OCTAL D FLIP-FLOP
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
Q0Q1Q2Q3Q4Q5Q6Q7
D0D1D2D3D4D5D6D7
CP
MR
相關(guān)PDF資料
PDF描述
MC74AC273N OCTAL D FLIP-FLOP
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