參數(shù)資料
型號(hào): MC74ACT113N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
中文描述: ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
封裝: PLASTIC, DIP-14
文件頁數(shù): 1/6頁
文件大?。?/td> 184K
代理商: MC74ACT113N
5-1
FACT DATA
The MC74AC113/74ACT113 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
Set is independent of clock
Outputs Source/Sink 24 mA
ACT113 Has TTL Compatible Inputs
11
12
VCC
14
CP1
K1
J1
SD1
Q1
Q1
CP2
13
K2
J2
SD2
10
Q2
9
Q2
CP
Q
GND
SD
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
Q
CP
K
Q
SD
Q
J
J
K
MODE SELECT — TRUTH TABLE
Operating Mode
Inputs
Outputs
SD
L
H
H
H
H
J
K
Q
Q
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
X
h
l
h
l
X
h
h
l
l
H
q
L
H
q
L
q
H
L
q
H, h = HIGH Voltage Level
L, l = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the HIGH to LOW clock transition.
DUAL JK NEGATIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 646-06
PLASTIC
D SUFFIX
CASE 751A-03
PLASTIC
LOGIC SYMBOL
SD
Q
J
CP
Q
VCC = PIN 14
GND = PIN 7
K
3
1
2
4
5
6
SD
Q
J
CP
Q
K
11
13
12
10
9
8
相關(guān)PDF資料
PDF描述
MC74ACT11D TRIPLE 3-INPUT AND GATE
MC74AC11 TRIPLE 3-INPUT AND GATE
MC74AC11D TRIPLE 3-INPUT AND GATE
MC74AC11N TRIPLE 3-INPUT AND GATE
MC74ACT11N TRIPLE 3-INPUT AND GATE
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