參數(shù)資料
型號: MC74AC646DW
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS (NON-INVERTING)
中文描述: AC SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 2/9頁
文件大?。?/td> 242K
代理商: MC74AC646DW
MC74AC646 MC74ACT646
5-2
FACT DATA
FUNCTION TABLE
Inputs
Data I/O*
Operation or Function
G
DIR
CAB
CBA
SAB
SBA
A0–A7
B0–B7
H
H
X
X
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
L
L
L
L
X
X
X
X
X
X
L
H
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real Time A Data to B Bus
Stored A Data to B Bus
* The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
1 OF 8 CHANNELS
D0
C0
D0
C0
CAB
SAB
DIR
CBA
SBA
G
B0
A0
TO 7 OTHER CHANNELS
LOGIC DIAGRAM
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
1
CAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12
GND
24
23
22
21
20
19
18
17
16
14
13
VCC
CBA
SBA
G
B0
B1
B2
B3
B4
B5
B6
B7
PIN NAMES
A0–A7
Data Register Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
B0–B7
CAB, CBA
SAB, SBA
DIR, G
15
相關(guān)PDF資料
PDF描述
MC74AC646DWR2 OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS (NON-INVERTING)
MC74AC646N OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS (NON-INVERTING)
MC74ACT646DW ECONOLINE: RBM - New Micro Size SIP 6 Package- Industry Standard Pinout- 3kVDC Isolation- UL94V-0 Package Material- Efficiency to 85%
MC74ACT646N OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS (NON-INVERTING)
MC74AC646N OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS (NON-INVERTING)
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