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參數(shù)資料
型號(hào): MC74AC573DWR2
廠商: ON Semiconductor
文件頁數(shù): 5/12頁
文件大小: 0K
描述: IC LATCH OCTAL 3ST 20-SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74AC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 6 V
獨(dú)立電路: 1
延遲時(shí)間 - 傳輸: 10ns
輸出電流高,低: 24mA,24mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 剪切帶 (CT)
其它名稱: MC74AC573DWR2OSCT
MC74AC573, MC74ACT573
http://onsemi.com
2
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
L
H
L
H
L
X
O0
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOWtoHIGH Transition of Clock
Functional Description
The MC74AC573/74ACT574 contains eight Dtype
latches with 3state output buffers. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGHtoLOW
transition of LE. The 3state buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Figure 3. Logic Diagram
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D1
D2
D3
D4
D5
D6
D7
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
D0
NOTE:
That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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