參數資料
型號: MC74AC377N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: OCTAL D FLIP-FLOP WITH CLOCK ENABLE
中文描述: AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
封裝: PLASTIC, DIP-20
文件頁數: 5/6頁
文件大?。?/td> 199K
代理商: MC74AC377N
MC74AC377 MC74ACT377
5-5
FACT DATA
AC CHARACTERISTICS
(For Figures and Waveforms — See Section 3)
Symbol
Parameter
(V)
74ACT
74ACT
Unit
No.
VCC*
TA = +25
°
C
CL = 50 pF
TA = –40
°
C
to +85
°
C
CL = 50 pF
Fig.
Min
Typ
Max
Min
Max
fmax
Maximum Clock
Frequency
5.0
140
125
MHz
3-3
tPLH
Propagation Delay
CP to Qn
Propagation Delay
CP to Qn
5.0
3.0
9.0
2.5
10
ns
3-6
tPHL
5.0
3.5
10
2.5
11
ns
3-6
* Voltage Range 5.0 V is 5.0 V
±
0.5 V.
AC OPERATING REQUIREMENTS
Symbol
Parameter
(V)
74ACT
74ACT
Unit
No.
VCC*
TA = +25
°
C
CL = 50 pF
TA = –40
°
C
to +85
°
C
CL = 50 pF
Fig.
Typ
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
Setup Time, HIGH or LOW
CE to CP
5.0
4.5
5.5
ns
3-9
th
5.0
1.0
1.0
ns
3-9
ts
5.0
4.5
5.5
ns
3-9
th
Hold Time, HIGH or LOW
CE to CP
5.0
1.0
1.0
ns
3-9
tw
CP Pulse Width
HIGH or LOW
5.0
4.0
4.5
ns
3-6
* Voltage Range 5.0 V is 5.0 V
±
0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
90
pF
VCC = 5.0 V
相關PDF資料
PDF描述
MC74ACT377N OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MC74ACT378D PARALLEL D REGISTER WITH ENABLE
MC74AC378 PARALLEL D REGISTER WITH ENABLE
MC74AC378D PARALLEL D REGISTER WITH ENABLE
MC74AC378N PARALLEL D REGISTER WITH ENABLE
相關代理商/技術參數
參數描述
MC74AC377NG 功能描述:觸發(fā)器 2-6V CMOS Octal D-Type Clock Enable RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
MC74AC378 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PARALLEL D REGISTER WITH ENABLE
MC74AC378D 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC74AC378N 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC74AC379 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad Parallel Register with Enable