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參數(shù)資料
型號: MC74AC373DWR2G
廠商: ON Semiconductor
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC LATCH OCT TRANSP 3ST 20SOIC
標準包裝: 1
系列: 74AC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 6 V
獨立電路: 1
延遲時間 - 傳輸: 7ns
輸出電流高,低: 24mA,24mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 標準包裝
其它名稱: MC74AC373DWR2GOSDKR
MC74AC373, MC74ACT373
http://onsemi.com
2
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
H
X
Z
L
H
L
H
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight Dtype
latches with 3state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGHtoLOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Figure 3. Logic Diagram
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D1
D2
D3
D4
D5
D6
D7
LE
OE
D0
NOTE:
This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
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