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參數(shù)資料
| 型號： | MC74AC253N |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | AC SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 182K |
| 代理商： | MC74AC253N |
MC74AC253, MC74ACT253
http://onsemi.com
2
TRUTH TABLE
Select
Inputs
Data Inputs
Output
Enable
Outputs
S0
S1
I0
I1
I2
I3
OE
Z
X
H
Z
L
X
L
H
X
L
H
L
X
L
X
L
H
L
X
H
X
L
H
L
H
X
L
X
L
H
X
H
X
L
H
X
L
H
X
H
L
H
Address inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
FUNCTIONAL DESCRIPTION
The MC74AC253/74ACT253 contains two identical
4input multiplexers with 3state outputs. They select two
bits from four sources selected by common Select inputs (S0,
S1). The 4input multiplexers have individual Output
Enable (OEa, OEb) inputs which, when HIGH, force the
outputs to a high impedance (High Z) state. This device is the
logic implementation of a 2pole, 4position switch, where
the position of the switch is determined by the logic levels
supplied to the two select inputs. The logic equations for the
outputs are shown:
Za = OEa(I0aS1S0+I1aS1S0+
I2aS1S0+I3aS1S0)
Zb = OEb(I0bS1S0+I1bS1S0+
I2bS1S0+I3bS1S0)
If the outputs of 3state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3state devices
whose outputs are tied together are designed so that there is
no overlap.
OEb
I3b
I2b
I1b
I0b
S0
S1
I3a
I2a
Zb
Za
I1a
I0a
OEa
NOTE: This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
Figure 2. Logic Symbol
S0
S1
OEa I0a I1a I2a I3a
Za
Zb
I0b I1b I2b I3b OEb
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