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參數(shù)資料
| 型號： | MC74AC112D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| 中文描述： | AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 191K |
| 代理商： | MC74AC112D |
5-1
FACT DATA
The MC74AC112/74ACT112 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Outputs Source/Sink 24 mA
′
ACT112 Has TTL Compatible Inputs
CP
J
VCC
16
CP1
K1
J1
SD1
Q1
Q1
CD1
15
CD2
14
CP2
13
K2
12
J2
11
SD2
10
CD
Q
Q2
SD
CONNECTION DIAGRAM
Q2
9
GND
1
2
3
4
5
6
7
8
K
Q
CP
K
SD
Q
CD
J
Q
MODE SELECT — TRUTH TABLE
Operating Mode
Inputs
Outputs
SD
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
H, h = HIGH Voltage Level
L, l = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the HIGH to LOW clock transition.
*Both outputs will be HIGH while both SD and CD are LOW, but the output states
DUAL JK NEGATIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
SD
Q
J
CP
Q
CD
VCC = PIN 16
GND = PIN 8
K
3
1
2
15
4
5
6
SD
Q
J
CP
Q
CD
K
11
13
12
14
10
9
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74AC112N | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74ACT112N | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74ACT113D | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74AC113D | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74AC113N | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC112N | 制造商:ON Semiconductor 功能描述: |
| MC74AC113D | 制造商:ONS 功能描述:ON SEMICONDUCTOR NXC6B |
| MC74AC113N | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| MC74AC11D | 功能描述:邏輯門 2-6V Triple 3-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74AC11DG | 功能描述:邏輯門 2-6V Triple 3-Input AND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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