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| 型號： | MC7447AVS867NB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 867MHZ 360-FCCLGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
26
Freescale Semiconductor
Pinout Listings
VDD_SENSE
G13, N12
—
N/A
18
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals; VDD supplies power to the processor core and the
PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V), or to
HRESET or OVDD (selects 2.5 V); see Table 3. If used, the pull-down resistor should be less than 250 Ω.Because these
settings may change in future products, it is recommended BVSEL be configured using resistor options, jumpers, or some
other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. For actual
2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OVDD.
3. These pins require weak pull-up resistors (for example, 4.7 K
Ω) to maintain the control signals in the negated state after they
have been actively negated and released by the MPC7447A and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull-up resistor to OVDD or negation by HRESET (inverse of HRESET), to
ensure proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the MPC7447A is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11.These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were
NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes.
12.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software.
14.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
15.These pins were NCs on the MPC7447, MPC7445, and MPC7441. They may be left unconnected for backward compatibility
with these devices, but it is recommended they be connected in new designs to facilitate future products. See Section 9.4,
“Connection Recommendations,” for more information.
16.These pins were OVDD pins on the MPC7447, MPC7445, and MPC7441. These pins are internally connected to OVDD and
are intended to allow an external device to detect the I/O voltage level present inside the device package. If unused, they
must be connected directly to OVDD or left unconnected.
17.These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature
of the processor. These pins may be left unterminated if unused.
18.These pins are internally connected to VDD and are intended to allow an external device to detect the processor core voltage
level present inside the device package. If unused, they must be connected directly to VDD or left unconnected.
19.These pins are internally connected to GND and are intended to allow an external device to detect the processor ground
voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.
Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select1
Notes
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