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| 型號： | MC7445ARX933LG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 933 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 44/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7445ARX933LG |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
49
System Design Information
The MPC7455 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7455. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7455 core, and timing analysis of the circuit
board routing. Table 18 shows various example L3 clock frequencies that can be obtained for a given set of
core frequencies.
11110
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:4] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7455; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold
time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
Table 18. Sample Core-to-L3 Frequencies
Core Frequency
(MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
500
250
200
167
143
125
100
83
533
266
213
178
152
133
107
89
550
275
220
183
157
138
110
92
600
300
240
200
171
150
120
100
6502
325
260
217
186
163
130
108
6662
333
266
222
190
167
133
111
7002
350
280
233
200
175
140
117
7332
367
293
244
209
183
147
122
8002
400
320
266
230
200
160
133
8672
433
347
289
248
217
173
145
9332
467
373
311
266
233
187
156
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts (continued)
PLL_
CFG[0:4]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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