參數(shù)資料
型號(hào): MC68S711E9CFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 34/242頁(yè)
文件大?。?/td> 1672K
代理商: MC68S711E9CFN2
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Timer Structure
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
129
9.2 Timer Structure
Figure 9-2 shows the capture/compare system block diagram. The port A pin control block includes logic
for timer functions and for general-purpose I/O. For pins PA3, PA2, PA1, and PA0, this block contains
both the edge-detection logic and the control logic that enables the selection of which edge triggers an
input capture. The digital level on PA[3:0] can be read at any time (read PORTA register), even if the pin
is being used for the input capture function. Pins PA[6:3] are used for either general-purpose I/O, or as
output compare pins. When one of these pins is being used for an output compare function, it cannot be
written directly as if it were a general-purpose output. Each of the output compare functions (OC[5:2]) is
related to one of the port A output pins. Output compare one (OC1) has extra control logic, allowing it
optional control of any combination of the PA[7:3] pins. The PA7 pin can be used as a general-purpose
I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.
9.3 Input Capture
The input capture function records the time an external event occurs by latching the value of the
free-running counter when a selected edge is detected at the associated timer input pin. Software can
store latched values and use them to compute the periodicity and duration of events. For example, by
storing the times of successive edges of an incoming signal, software can determine the period and pulse
width of a signal. To measure period, two successive edges of the same polarity are captured. To
measure pulse width, two alternate polarity edges are captured.
In most cases, input capture edges are asynchronous to the internal timer counter, which is clocked
relative to an internal clock (PH2). These asynchronous capture requests are synchronized to PH2 so that
the latching occurs on the opposite half cycle of PH2 from when the timer counter is being incremented.
This synchronization process introduces a delay from when the edge occurs to when the counter value is
detected. Because these delays offset each other when the time between two edges is being measured,
the delay can be ignored. When an input capture is being used with an output compare, there is a similar
delay between the actual compare point and when the output pin changes state.
Table 9-1. Timer Summary
XTAL Frequencies
Control Bits
PR1, PR0
4.0 MHz
8.0 MHz
12.0 MHz
Other Rates
1.0 MHz
2.0 MHz
3.0 MHz
(E)
1000 ns
500 ns
333 ns
(1/E)
Main Timer Count Rates
0 0
1 count —
overflow —
1000 ns
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
(E/1)
(E/216)
0 1
1 count —
overflow —
4.0
s
262.14 ms
2.0
s
131.07 ms
1.333
s
87.381 ms
(E/4)
(E/218)
1 0
1 count —
overflow —
8.0
s
524.29 ms
4.0
s
262.14 ms
2.667
s
174.76 ms
(E/8)
(E/219)
1 1
1 count —
overflow —
16.0
s
1.049 s
8.0
s
524.29 ms
5.333
s
349.52 ms
(E/16)
(E/220)
相關(guān)PDF資料
PDF描述
MC68HC11E9MPB2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP52
MC68HC711E9CFS2 8-BIT, UVPROM, 2 MHz, MICROCONTROLLER, CQCC52
MC68L11E1PB2 8-BIT, 2 MHz, MICROCONTROLLER, PQFP52
MC68HC11E9VFU2 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
MC68HC711E20CFN2 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQCC52
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MC68SEC000AA10R2 功能描述:IC MPU 32BIT 10MHZ 64-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA(25x25) 包裝:托盤
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MC68SEC000AA16 制造商:Freescale Semiconductor 功能描述:Microprocessor