- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1949 > MC68LC060RC66 (Freescale Semiconductor)IC MPU 32BIT 66MHZ 206-PGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68LC060RC66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 80/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁當(dāng)前第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-9
2.4.1 Transfer Start (TS)
The processor asserts this three-state bidirectional signal for one clock-enabled clock period
to indicate the start of each bus cycle. During alternate bus master accesses, the processor
monitors TS and SNOOP to detect the start of each bus cycle which is to be snooped. TS
is placed in a high-impedance state when the MC68060 is not the bus master. To properly
maintain internal state information, all masters on the bus must have their TS signals tied
together.
2.4.2 Transfer in Progress (TIP)
This three-state output is asserted to indicate that a bus cycle is in progress and is negated
during idle bus cycles if the bus is still granted to the processor. TIP remains asserted during
the time between back-to-back bus cycles.
If the MC68060 relinquishes the bus while TIP is asserted, TIP will be negated for one clock
period after completion of the final transfer and then goes to a high-impedance state one
clock period after the address is idled. Note that this one clock period in which TIP is driven
negated refers to an MC68060 processor clock period, not a full clock-enabled clock period.
If TIP was already negated in the clock period in which the MC68060 relinquishes the bus,
it will be placed in a high-impedance state in the same clock period that the address bus
becomes idle.
2.4.3 Starting Termination Acknowledge Signal Sampling (SAS)
This three-state output is asserted for one clock-enabled clock period to indicate that the
MC68060 will begin sampling TA, TEA, TRA, TBI, TCI, AVEC, and spurious interrupt indi-
cation on the next rising edge of the clock-enabled clock. SAS is negated at all other times
while the MC68060 is the bus master. When the MC68060 relinquishes the bus, SAS is
driven negated for one clock-enabled clock period and then three-stated one clock-enabled
clock period after the address bus is idled. When the MC68060 newly gains bus ownership
and immediately starts a bus cycle with the assertion of TS, SAS remains three-stated until
the clock-enabled clock period after TS is asserted.
2.5 SLAVE TRANSFER CONTROL SIGNALS
The following signals provide control functions for bus transfers when the MC68060 is not
the bus master. Refer to Section 7 Bus Operation for detailed information about the rela-
tionship of the bus cycle control signals to bus operation.
2.5.1 Transfer Acknowledge (TA)
This input indicates the completion of a requested data transfer operation. During transfers
by the MC68060, TA is an input signal from the referenced slave device indicating comple-
tion of the transfer. For the MC68060 to accept the transfer as successful with a transfer
acknowledge, TRA and TEA must be negated when TA is asserted.
2.5.2 Transfer Retry Acknowledge (TRA)
For native-MC68060-style (non-MC68040-style) acknowledge termination, this input signal
may be asserted by the current slave on the first transfer of a bus cycle to indicate the need
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68LC060ZU75 | IC MPU 32BIT 68K 75MHZ 304-TBGA |
| MC68M360ZQ25VLR2 | IC MPU QUICC 25MHZ 357-PBGA |
| MC68MH360CZQ25L | IC MPU QUICC 25MHZ 357-PBGA |
| MC68P11E1CFNE2R | IC MCU 8BIT 52-PLCC |
| MC68SEC000AA16R2 | IC MPU 32BIT 16 MHZ 64-QFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68LC060RC75 | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC060ZU50 | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC060ZU66 | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC060ZU75 | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC302AF16CT | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 68K INTGR COM PROC, DMA RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。