參數(shù)資料
型號(hào)： MC68L11K4FU1
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 27/80頁(yè)
文件大小： 420K
代理商： MC68L11K4FU1
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
27
4 Memory Expansion and Chip Selects
Two additional on-chip blocks are provided with the M68HC11 K-series MCUs. The first block imple-
ments additional address lines that become active only when required by the CPU. The second block
provides chip-select signals that simplify the interface to external peripheral devices. Both of these
blocks are fully programmable by values written to associated control registers.
4.1 Memory Expansion
New to the M68HC11 family of microcontrollers is the ability of the M68HC11 K-series MCUs to extend
the address range of the M68HC11 CPU beyond the physical 64 Kbyte limit of the 16 CPU address
lines. The following is a brief description of how the extended addressing is achieved. For a more de-
tailed discussion refer to application note Using the MC68HC11K4 Memory Mapping Logic(AN452/D).
Memory expansion is achieved by manipulating the CPU address lines such that, even though the CPU
cannot distinguish more than 64 Kbytes of physical memory, up to 1 Mbyte can be accessed through a
paged memory scheme. Additional address lines XA[18:13] are provided as alternate functions of port
G pins. Bits in the port G assignment register (PGAR) define which port G pins are to be used for mem-
ory expansion address lines and which are to be used for general-purpose I/O.
In order to access expanded memory, the user must first allocate a range of the 64 Kbyte address space
to be used for the window(s) through which external expanded memory is viewed by the CPU. The size
and placement of the window(s) depend upon values written to the MMSIZ and MMWBR registers, re-
spectively. Which bank or page of the expanded memory that is present in the window(s) at a given time
is dependent upon values written to the MM1CR and MM2CR registers.
Up to two windows can be designated and each can be programmed to 0 (disabled), 8, 16, or 32 Kbytes.
The base address for each window must be an integer multiple of the window size. When the window
size is 32 Kbytes, the base address can be at $0000, $4000, or $8000.
If the windows are defined in such a way that they overlap, bank window 1 has priority and the part of
window 2 that is not overlapped by bank window 1 remains active. If a window is defined such that it
overlaps any internal registers, RAM, or EEPROM, the portion of the registers, RAM, or EEPROM that
is overlapped is repeated in all banks associated with that window. However, if ROM/EPROM is en-
abled and overlapped by a window, the ROM/EPROM is present only in banks with XA[18:16] = 0:0:0.
Expanded memory is addressed by using a combination of the CPU's normal address lines ADDR[15:0]
and the expansion address lines XA[18:13]. Window size and the number of banks associated with the
window determine exactly which address lines are used. The additional address lines (XA[18:13]) de-
termine which bank is present in a window at a given time. The lower three expansion address lines
(XA[15:13]) are used only when needed by the CPU and replace the CPU's equivalent address lines
(ADDR[15:13]). The following tables show which address lines are used for various configurations of
expanded memory.
Five registers control operation of the memory expansion function. MM1CR and MM2CR registers in-
dicate which bank of a window is active. Each contains the value to be output when the CPU selects
addresses within the memory expansion window. PGAR selects which pins are used for I/O or memory
expansion address lines, defining which extended address lines are used. The MMWBR register de-
fines the starting address of each of the two windows within the CPU 64-Kbyte address range. The MM-
SIZ register sets the size of the windows in use and selects whether the on-board general-purpose chip
selects are active for CPU addresses or for expansion addresses.
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