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參數(shù)資料
| 型號： | MC68L11K1FN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 47/80頁 |
| 文件大小： | 420K |
| 代理商： | MC68L11K1FN3 |
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M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
47
NOTE
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to
4.3 Memory
Expansion and Chip Selects
and
12 Pulse-Width Modulation Timer
for further
information.
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
DDG[7:0] —Data Direction for Port G
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
Bits [7:6] —Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
NOTE
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to
4.1 Memory Ex-
pansion
for further information.
PORTG
—Port G Data
$007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
DDRG
—Data Direction Register for Port G
$007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
RESET:
0
0
0
0
0
0
0
0
PGAR
—
Port G Assignment
$002D
Bit 7
6
5
4
3
2
1
Bit 0
$
0
02D
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
RESET:
0
0
0
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68L11K1FUE2 | 功能描述:8位微控制器 -MCU 8B MCU L-VOLTAGE-EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68L711E9FN2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68L711E9FNE2 | 功能描述:8位微控制器 -MCU 8B MCU LO VOLTAGE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68L711E9FU2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68L711M2CFU | 制造商:Freescale Semiconductor 功能描述: |
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