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  • 參數(shù)資料
    型號: MC68L11K1FN1
    廠商: MOTOROLA INC
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT MICROCONTROLLER
    中文描述: 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQCC84
    封裝: PLASTIC, LCC-84
    文件頁數(shù): 44/80頁
    文件大?。?/td> 420K
    代理商: MC68L11K1FN1
    MOTOROLA
    44
    M68HC11 K Series
    MC68HC11KTS/D
    LIRDV—LIR Driven
    Refer to
    2 Operating Modes
    .
    CWOM —Port C Wired-OR Mode
    0 = Port C operates normally.
    1 = Port C outputs are open-drain.
    Bit 5 —Not implemented
    Always read zero
    IRVNE —Internal Read Visibility/Not E
    Refer to
    2 Operating Modes
    .
    LSBF —SPI LSB First Enable
    Refer to
    8 Serial Peripheral Interface
    .
    SPR2 —SPI Clock (SCK) Rate Select
    Refer to
    8 Serial Peripheral Interface
    .
    XDV[1:0] —XOUT Clock Divide Select
    Refer to
    2 Operating Modes
    .
    Bits [7:6] — Not implemented
    Always read zero
    DDD[5:0] — Data Direction for Port D
    0 = Corresponding pin configured for input
    1 = Corresponding pin configured for output
    NOTE
    When the SPI system is in slave mode, DDD5 has no meaning nor effect. When
    the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an
    error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI
    system is enabled and expects any of bits [4:2] to be an input that bit will be an input
    regardless of the state of the associated DDR bit. If any of bits [4:2] are expected
    to be outputs that bit will be an output
    only
    if the associated DDR bit is set.
    OPT2
    —System Configuration Options 2
    $0038
    Bit 7
    LIRDV
    0
    6
    5
    0
    4
    3
    2
    1
    Bit 0
    XDV0
    0
    CWOM
    0
    IRVNE
    LSBF
    0
    SPR2
    0
    XDV1
    0
    RESET:
    PORTD
    —Port D Data
    $0008
    Bit 7
    0
    6
    0
    5
    4
    3
    2
    1
    Bit 0
    PD0
    I
    PD5
    I
    PD4
    I
    PD3
    I
    PD2
    I
    PD1
    I
    RESET:
    Alt. Pin
    Func.:
    SS
    SCK
    MOSI
    MISO
    TxD
    RxD
    DDRD
    —Data Direction Register for Port D
    $0009
    Bit 7
    0
    6
    0
    5
    4
    3
    2
    1
    Bit 0
    DDD0
    0
    DDD5
    0
    DDD4
    0
    DDD3
    0
    DDD2
    0
    DDD1
    0
    RESET:
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