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參數(shù)資料
| 型號(hào)： | MC68L11F1PU3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, EEPROM, MICROCONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 51/68頁 |
| 文件大?。?/td> | 486K |
| 代理商： | MC68L11F1PU3 |
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MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
51
SPR[1:0] — SPI Clock Rate Selects
These two bits select the SPI clock (SCK) rate when the device is configured as a master. When the
device is configured as a slave, the bits have no effect. Refer to
Table 23
.
NOTE
The SPRBYP bit in OPT2 on the MC68HC11FC0 allows the SPI baud rate counter
to be bypassed. This permits a maximum master mode baud rate equal to the E-
clock frequency on the MC68HC11FC0.
SPRBYP is not present on the
MC68HC11F1
.
SPIF — SPI Transfer Complete Flag
SPIF is set when an SPI transfer is complete. It is cleared by reading SPSR with SPIF set, followed by
a read or write of SPDR.
WCOL — Write Collision
WCOL is set when SPDR is written while a transfer is in progress. It is cleared by reading SPSR with
WCOL set, followed by a read or write of SPDR.
0 = No write collision
1 = Write collision
Bit 5 — Not Implemented. Reads always return zero and writes have no effect.
MODF — Mode Fault
A mode fault terminates SPI operation. Set when SS is pulled low while MSTR = 1. MODF is cleared
by reading SPSR read with MODF set, followed by a write to SPCR.
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not Implemented. Reads always return zero and writes have no effect.
Incoming SPI data is double buffered. Outgoing SPI data is single buffered.
Table 23 SPI Baud Rates
Input
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
SPR[1:0] = 00
SPR[1:0] = 01
SPR[1:0] = 10
SPR[1:0] = 11
500 kbps
1 Mbps
1.5 Mbps
2 Mbps
2.5 Mbps
3 Mbps
E/2
250 kbps
500 kbps
750 kbps
1 Mbps
1.25 Mbps
1.5 Mbps
E/4
62.5 kbps
125 kbps
187.5 kbps
250 kbps
312.5 kbps
375 kbps
E/16
31.25 kbps
62.5 kbps
93.75 kbps
125 kbps
156.25 kbps
187.5 kbps
E/32
SPSR —
SPI Status Register
$x029
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
SPDR —
SPI Data
Register
$x02A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
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