參數(shù)資料
型號: MC68L11F1FN3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Multiconductor Audio, Control & Instrumentation Cable; Number of Conductors:15; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Material:Polyvinylchloride (PVC); Conductor Material:Copper; Conductor Plating:Tin RoHS Compliant: Yes
中文描述: 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 23/68頁
文件大小: 486K
代理商: MC68L11F1FN3
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
23
CWOM — Port C Wired-OR Mode Option
Refer to
7.8 Parallel I/O Registers
, page 37.
CLK4X — 4XCLK Output Enable
This bit can only be written once after reset in all modes.
0 = 4XOUT clock output is disabled
1 = Buffered oscillator is driven on the 4XOUT clock output
LIRDV — Load Instruction Register Driven
In order to detect consecutive instructions in a high-speed application, LIR can be driven high for one
quarter of an E-clock cycle during each instruction fetch.
0 = LIR signal is not driven high.
1 = LIR signal is driven high.
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP
See
10.2 SPI Registers
, page 52.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU — A/D Power-Up
. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D system disabled
1 = A/D system enabled
CSEL — Clock Select
This bit is implemented on the MC68HC11F1 only
. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
IRQE — IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay of 4064 E-clock cycles is enabled on exit from STOP
CME — Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME — Force Clock Monitor Enable
0 = Clock monitor circuit follows the state of the CME bit
1 = Clock monitor circuit is enabled until the next reset
In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executing
a STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the
user intends to use the STOP instruction.
CR[1:0] — COP Timer Rate Select
Refer to
5.2 Reset and Interrupt Registers
, page 27.
OPTION —
System Configuration Options
$x039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
RESET:
0
0
0
1
0
0
0
0
相關(guān)PDF資料
PDF描述
MC68L11F1PU3 Technical Summary 8-Bit Microcontroller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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