參數(shù)資料
型號： MC68L11D0FN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 6/131頁
文件大?。?/td> 1640K
代理商： MC68L11D0FN2
MC68HC11D3
TIMING SYSTEM
MOTOROLA
TECHNICAL DATA
9-17
9.6.1 Pulse Accumulator Control Register
Four of this register's bits control an 8-bit pulse accumulator system. Another bit en-
ables either the OC5 function or the IC4 function, while two other bits select the rate
for the real-time interrupt system.
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used
as general-purpose I/O or as an output compare. Note that even when port A bit 7 is
configured as an output, the pin still drives the input to the pulse accumulator. Refer to
SECTION 6 PARALLEL I/O for more information.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
the following table:
DDRA3 — Data Direction Register for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5
RTR[1:0] — RTI Interrupt Rate Selects
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
PACTL — Pulse Accumulator Control
$0026
Bit 7
654321
Bit 0
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
RESET:
0000000
0
PAMOD
PEDGE
Action on Clock
0
PAI Falling Edge Increments the Counter.
0
1
PAI Rising Edge Increments the Counter.
1
0
A Zero on PAI Inhibits Counting.
1
A One on PAI Inhibits Counting.
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參數(shù)描述
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