參數(shù)資料
型號： MC68L11D0CFB3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 2 MM HEIGHT, 0.80 MM PITCH, QFP-44
文件頁數(shù)： 4/131頁
文件大?。?/td> 1640K
代理商： MC68L11D0CFB3
MC68HC11D3
TIMING SYSTEM
MOTOROLA
TECHNICAL DATA
9-15
RTR[1:0] — RTI Interrupt Rate Select
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 213 rate clock that is compensated so it is in-
dependent of the timer prescaler. These two control bits select an additional division
factor.
9.5 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. Refer to SECTION 5 RESETS AND INTERRUPTS for a more detailed dis-
cussion of the COP function.
9.6 Pulse Accumulator
The MC68HC11D3 has an 8-bit counter that can be configured to operate either as a
simple event counter, or for gated time accumulation, depending on the state of the
PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Fig-
In the event counting mode, the 8-bit counter is clocked to increasing values by an ex-
ternal pin. The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock
÷ 64
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer to
Table 9-3. The pulse accumulator counter can be read or written at any time.
RTR[1:0]
E = 1 MHz
E = 2 MHz
E = 3 MHz
E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
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