參數(shù)資料
型號： MC68L11D0CFB2R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 2 MM HEIGHT, 0.80 MM PITCH, QFP-44
文件頁數(shù)： 92/131頁
文件大?。?/td> 1640K
代理商： MC68L11D0CFB2R2
MC68HC11D3
PARALLEL I/O
MOTOROLA
TECHNICAL DATA
6-1
SECTION 6
PARALLEL I/O
The MC68HC11D3 has four 8-bit I/O ports; A, B, C, and D. In single-chip and bootstrap
modes, all ports are parallel I/O data ports. In expanded multiplexed and test modes,
ports B and C, and lines DATA6/AS and DATA7/R/W are a memory expansion bus
with port B as the high order address bus, port C as the multiplexed address and data
bus, AS as the demultiplexing signal, and R/W as the data bus direction control. Refer
to Table 6-1, which is a summary of the ports and their shared functions:
6.1 Port A
Port A bits handle the timer functions and can also be used as general-purpose I/O. In
both the normal operating modes, port A can be configured for four timer input capture
(IC) and three timer output compare (OC) functions, or four OC and three IC functions
with either a pulse accumulator input (PAI) or a fifth OC function.
*This pin is not bonded in the 40-pin version.
6.2 Port B
In single-chip mode, all port B pins are general-purpose I/O (PB[7:0]). In expanded
multiplexed mode, all port B pins act as high-order address bits (ADDR[15:8]).
Table 6-1 I/O Ports
Port
Input Pins
Output Pins
Bidirectional Pins
Shared Functions
Port A
3
2
TImer
Port B
—
8
High Order Address
Port C
—
8
Low Order Address and Data Bus
Port D
—
8
SCI, SPI, AS, and R/
PORTA — Port A Data
$0000
Bit 7
654321
Bit 0
PA7
PA6*
PA5
PA4*
PA3
PA2
PA1
PA0
RESET:
HiZ
0
HiZ
Alt. Func:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
—
PORTB — Port B Data
$0004
Bit 7
654321
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip
or Boot:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
Reset configures pins as HiZ inputs
Expan.
or Test:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
RESET:
Reset configures pins as high-order address outputs
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