參數(shù)資料
型號(hào): MC68HSR705J1ACPE
廠商: Freescale Semiconductor
文件頁數(shù): 8/162頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 64 BYTES RAM 20-PDIP
標(biāo)準(zhǔn)包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
External Interrupt Module (IRQ)
Operation
MC68HC705J1A — Rev. 4.0
Technical Data
External Interrupt Module (IRQ)
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE:
The branch if interrupt pin is high (BIH) and branch if interrupt pin is low
(BIL) instructions apply only to the level on the IRQ/VPP pin itself and not
to the output of the logic OR function with the PA0–PA3 pins. The state
of the individual port A pins can be checked by reading the appropriate
port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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