參數資料
型號: MC68HSC705J1AP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數: 142/162頁
文件大?。?/td> 3213K
代理商: MC68HSC705J1AP
Technical Data
MC68HC705J1A — Rev. 4.0
Low-Power Modes
Low-Power Modes
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
5.3 Exiting Stop and Wait Modes
The events described in this subsection bring the MCU out of stop mode
and load the program counter with the reset vector or with an interrupt
vector.
Exiting stop mode:
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Exiting wait mode:
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
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相關PDF資料
PDF描述
MC68HC705J1ACPE 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC705J1ACS 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
MC68HSR705J1ACDW 8-BIT, OTPROM, MICROCONTROLLER, PDSO20
MC68HC705J1AVS 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
MC68HSC705J1ACS 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CDIP20
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