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參數(shù)資料
| 型號(hào)： | MC68HSC05P1ADWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 87/124頁(yè) |
| 文件大小： | 623K |
| 代理商： | MC68HSC05P1ADWR2 |
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16-Bit Timer
Timer
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
16-Bit Timer
65
NON-DISCLOSURE
AGREEMENT
REQUIRED
NOTE:
The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time that
the high and low bytes are accessed.
8.3 Timer
The key element of the programmable timer is a 16-bit free-running
counter, or timer registers, preceded by a prescaler, which divides the
PH2 clock by four. The prescaler gives the timer a resolution of 2.0
microseconds when a 4-MHz crystal is used. The counter is incremented
to increasing values during the low portion of the PH2 clock cycle.
The double-byte, free-running counter can be read from either of two
locations: the timer registers (TMRH and TMRL) or the alternate counter
registers (ACRH and ACRL). Both locations will contain identical values.
A read sequence containing only a read of the least significant bit (LSB)
of the counter (TMRL/ACRL) will return the count value at the time of the
read. If a read of the counter accesses the most significant bit (MSB) first
(TMRH/ACRH), it causes the LSB (TMRL/ACRL) to be transferred to a
buffer. This buffer value remains fixed after the first MSB byte read even
if the MSB is read several times. The buffer is accessed when reading
the counter LSB (TMRL/ACRL), and thus completes a read sequence of
the total counter value. When reading either the timer or alternate
counter registers, if the MSB is read, the LSB must also be read to
complete the read sequence. See Figure 8-2 and Figure 8-3.
The timer registers and alternate counter registers can be read at any
time without affecting their value. However, the alternate counter
registers differ from the timer registers in one respect: A read of the timer
register MSB can clear the timer overflow flag (TOF). Therefore, the
alternate counter registers can be read at any time without the possibility
of missing timer overflow interrupts due to clearing of the TOF. See
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|---|---|
| MC68HCL05P1ADWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P1P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P3CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC05P3P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05P3CP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
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