參數(shù)資料
型號(hào)： MC68HSC05K0DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 123/154頁
文件大小： 1544K
代理商： MC68HSC05K0DW
Technical Data
MC68HC05K0 MC68HC05K1 — Rev. 2.0
70
Parallel Input/Output (I/O)
MOTOROLA
Technical Data
When a port A pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port A pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit. Table 7-1 summarizes the
operations of the port A pins.
7.4 Port B
Port B is a 2-bit, general-purpose, bidirectional I/O port with these
features:
Programmable pulldown devices (mask option)
Oscillator output for 3-pin resistor-capacitor (RC) oscillator mask
option
7.4.1 Port B Data Register
The port B data register (PORTB), shown in Figure 7-5, contains a bit
for each of the port B pins. When a port B pin is programmed to be an
output, the state of its data register bit determines the state of the output
pin. When a port B pin is programmed to be an input, reading the port B
Table 7-1. Port A Pin Functions
Pulldown
Mask
Option
Control Bits
I/O Pin Mode
Accesses
to PDRA
Accesses
to DDRA
Accesses
to PORTA
PDIAx
DDRAx
Read
Write
Read/Write
Read
Write
No
X
0
Input, hi-z
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
No
X
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
Yes
0
Input,
pulldown on
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
Yes
0
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
Yes
1
0
Input, hi-z
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
Yes
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
X = Don’t care
U = Undefined
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