參數(shù)資料
型號： MC68HSC05J1ADW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 69/128頁
文件大?。?/td> 1650K
代理商： MC68HSC05J1ADW
Interrupts
Interrupt Sources
MC68HC05J1A — Rev. 3.0
Technical Data
Interrupts
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR), shown in Figure 4-2,
contains an external interrupt mask, an external interrupt flag, and a flag
reset bit.
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Resets set the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Resets clear the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQ flag:
a. An external interrupt signal on the IRQ pin
b. An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
The CPU clears the IRQ flag when fetching the interrupt vector.
Writing to the IRQ flag has no effect. Clear the IRQ flag by writing a
logic 1 to the IRQR bit.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the IRQ flag.
1 = IRQF bit cleared
0 = No effect
Address:
$000A
Bit 7
6
54321
Bit 0
Read:
IRQE
IRQF
0000
0
Write:
IRQR
Reset:
10
000000
= Unimplemented
Figure 4-2. IRQ Status and Control Register (ISCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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