Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
89
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR flag is set and the FE flag is not set. Clear the
FE bit by reading the SCSR and then reading the SCDR.
1 = Framing error
0 = No framing error
9.12.5 Baud Rate Register
The baud rate register (BAUD), shown in Figure 9-12, selects the baud
rate for both the receiver and the transmitter.
SCP1 — SCP0–SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0.
Address: $000D
Bit 7
6543
2
1
Bit 0
Read:
SCP1
SCP0
SCR2
SCR1
SCR0
Write:
Reset:
——
00
—
UUU
= Unimplemented
U = Unaffected
Figure 9-12. Baud Rate Register (BAUD)
Table 9-1. Baud Rate Generator
Clock Prescaling
SCP1 and SCP0
Baud Rate
Generator Clock
0 0
Internal clock
÷ 1
0 1
Internal clock
÷ 3
1 0
Internal clock
÷ 4
1 1
Internal clock
÷ 13
