參數(shù)資料
型號： MC68HSC05C8CFN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 58/116頁
文件大小： 781K
代理商： MC68HSC05C8CFN
Timer
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
46
Freescale Semiconductor
8.6 Timer Status Register
The timer status register (TSR) is a read-only register containing three status flag bits.
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($15) are accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-running counter contents
0 = Flag cleared when TSR and output compare low register ($17) are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running counter at
random times to measure an elapsed time. Without incorporating the proper precautions into software,
the timer overflow flag could unintentionally be cleared if:
1.
The timer status register is read or written when TOF is set.
2.
The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the same value as the free-running
counter (at address $18 and $19); therefore, this alternate register can be read at any time without
affecting the timer overflow flag in the timer status register.
8.7 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, the timer remains active. If interrupts are
enabled, a timer interrupt will cause the processor to exit the wait mode.
8.8 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If
reset is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs
at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up
the microcontroller unit (MCU). But if the MCU exits stop due to an external interrupt, there is an active
input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used
to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
U = Unaffected
Figure 8-4. Timer Status Register (TSR)
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