參數(shù)資料
型號： MC68HSC05C8CB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
封裝： SHRINK, PLASTIC, DIP-42
文件頁數(shù)： 22/166頁
文件大小： 1914K
代理商： MC68HSC05C8CB
Instruction Set
Technical Data
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
118
Instruction Set
MOTOROLA
12.6 Opcode Map
TAX
Transfer Accumulator to Index Register
X
← (A)
— ————
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
(M) – $00
——
—
DIR
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
5
4
TXA
Transfer Index Register to Accumulator
A
← (X)
— ————
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 ———
INH
8F
2
A
Accumulator
opr
Operand (one or two bytes)
C
Carry/borrow flag
PC
Program counter
CCR
Condition code register
PCH
Program counter high byte
dd
Direct address of operand
PCL
Program counter low byte
dd rr
Direct address of operand and relative offset of branch instruction
REL
Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
rr
Relative program counter offset byte
EXT
Extended addressing mode
SP
Stack pointer
ff
Offset byte in indexed, 8-bit offset addressing
X
Index register
H
Half-carry flag
Z
Zero flag
hh ll
High and low bytes of operand address in extended addressing
#
Immediate value
I
Interrupt mask
∧
Logical AND
ii
Immediate operand byte
∨
Logical OR
IMM
Immediate addressing mode
⊕
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
–( )
Negation (two’s complement)
IX1
Indexed, 8-bit offset addressing mode
←
Loaded with
IX2
Indexed, 16-bit offset addressing mode
?
If
M
Memory location
:
Concatenated with
N
Negative flag
Set or cleared
n
Any bit
—
Not affected
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
Source
Form
Operation
Description
Effect
on CCR
Address
Mode
Opc
o
de
Ope
rand
Cy
cl
es
HIN Z C
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