
Electrical Specifications
Technical Data
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
134
Electrical Specifications
MOTOROLA
Figure 13-9. SPI Master Timing Diagram
NOTE
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
SS PIN OF MASTER HELD HIGH.
MSB IN
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
NOTE
4
5
1
13
12
4
12
13
BITS 6–1
LSB IN
MASTER MSB OUT
BITS 6–1
MASTER LSB OUT
10 (REF)
13
11
10
12
11 (REF)
7
6
NOTE
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
SS PIN OF MASTER HELD HIGH.
MSB IN
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
NOTE
4
5
1
13
12
4
13
BITS 6–1
LSB IN
MASTER MSB OUT
BITS 6–1
MASTER LSB OUT
10 (REF)
13
11
10
12
11
7
6
12
a) SPI Master Timing (CPHA = 0)
b) SPI Master Timing (CPHA = 1)
12